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oki semiconductor fedd51x17400f-03 issue date: aug. 16, 2002 msm51x17400f 4,194,304-word 4-bit dynamic ram : fast page mode type 1/13 description the msm51x17400f is a 4,194,304-word 4-bit dynamic ram fabricated in oki?s silicon-gate cmos technology. the msm51x17400f achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/double-layer metal cmos process. the msm 51x17400f is available in a 26/24-pin plastic tsop. features 4,194,304-word 4-bit configuration single 2.0v power supply, 0.15v tolerance input : cmos interface, low input capacitance output : cmos interface, 3-state refresh : 2048 cycles/32ms fast page mode, read modify write capability cas before ras refresh capability packages 26/24-pin 300mil plastic tsop ( tsopii26/24-p-300-1.27-k ) (product : msm51x17400f-xxts-k) xx indicates speed rank. product family access time (max.) power dissipation family t rac t aa t cac t oea cycle time (min.) operating (max.) standby (max.) msm51x17400f-10 100ns 50ns 20ns 20ns 200ns 200mw 1.1mw
fedd51x17400f-03 1 semiconductor msm51x17400f 2/13 pin configuration (top view) pin name function a0?a10 address input ras row address strobe cas column address strobe dq1?dq4 data input/data output oe output enable we write enable v cc power supply v ss ground (0v) nc no connection note : the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin. 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 dq1 dq2 v cc v cc v ss v ss dq4 dq3 a9 a8 a7 a6 a0 a1 a2 a3 we ras nc a10 a5 a4 cas oe 26/24-pin plastic tsop (k type)
fedd51x17400f-03 1 semiconductor msm51x17400f 3/13 block diagram 4 4 4 4 4 4 11 11 11 11 timing generator column address buffers internal address counter row address buffers refresh control clock column decoders sense amplifiers memory cells word drivers row deco- ders i/o selector input buffers output buffers dq1 ? dq 4 oe we ras cas v cc v ss on chip v bb generator timing generator 4 write clock generator a0 ? a10
fedd51x17400f-03 1 semiconductor msm51x17400f 4/13 electrical characteristics absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in , v out ?0.5 to v cc + 0.5 v voltage v cc supply relative to v ss v cc ?0.5 to 3.0 v short circuit output current i os 50 ma power dissipation p d* 1 w operating temperature t opr ?10 to 70 c storage temperature t stg ?55 to 150 c *: ta = 25 c recommended operating conditions (ta = ?10 to 70c) parameter symbol min. typ. max. unit v cc 1.85 2.0 2.15 v power supply voltage v ss 0 0 0 v input high voltage v ih 0.8 v cc ? v cc + 0.2 v input low voltage v il ? 0.2 ? 0.2 v cc v pin capacitance (v cc = 2.0v 0.15v, ta = 25c, f = 1 mhz) parameter symbol min. max. unit input capacitance (a0 ? a10) c in1 ? 5 pf input capacitance ( ras , cas , we , oe ) c in2 ? 7 pf output capacitance (dq1 ? dq4) c i/o ? 7 pf
fedd51x17400f-03 1 semiconductor msm51x17400f 5/13 dc characteristics (v cc = 2.0v 0.15v, ta = ?10 to 70c) msm51x17400 f-10 parameter symbol condition min. max. unit note input high voltage v ih 0.8 v cc v cc + 0.2 v input low voltage v il ? 0.2 0.2 v cc v output high voltage v oh i oh = ? 100 a 0.85 v cc v cc v output low voltage v ol i ol = 100 a 0 0.15 v cc v input leakage current i li 0v v i v cc ; all other pins not under test = 0v ? 10 10 a output leakage current i lo dq disable 0v v o v cc ? 10 10 a average power supply current (operating) i cc1 ras , cas cycling, t rc = min. ? 90 ma 1,2 ras , cas = v ih ? 2 power supply current (standby) i cc2 ras , cas v cc ? 0.2v ? 0.5 ma 1 average power supply current ( cas before ras refresh) i cc6 ras = cycling, cas before ras ? 90 ma 1,2 average power supply current (fast page mode) i cc7 ras = v il , cas cycling, t pc = min. ? 90 ma 1,3 notes: 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih .
fedd51x17400f-03 1 semiconductor msm51x17400f 6/13 ac characteristics (1/2) (v cc = 2.0v 0.15v, ta = ?10 to 70c) note 1,2,3 msm51x17400 f-10 parameter symbol min. max. unit note random read or write cycle time t rc 200 ? ns fast page mode cycle time t pc 60 ? ns access time from ras t rac ? 100 ns 4, 5, 6 access time from cas t cac ? 20 ns 4, 5 access time from column address t aa ? 50 ns 4, 6 access time from cas precharge t cpa ? 55 ns 4 access time from oe t oea ? 20 ns 4 output low impedance time from cas t clz 0 ? ns 4 cas to data output buffer turn-off delay time t off 0 25 ns 7 oe to data output buffer turn-off delay time t oez 0 25 ns 7 transition time t t 3 50 ns 3 refresh period t ref ? 32 ms ras precharge time t rp 60 ? ns ras pulse width t ras 100 10,000 ns ras pulse width (fast page mode) t rasp 100 100,000 ns ras hold time t rsh 20 ? ns ras hold time referenced to oe t roh 20 ? ns cas precharge time (fast page mode) t cp 15 ? ns cas pulse width t cas 20 10,000 ns cas hold time t csh 70 ? ns cas to ras precharge time t crp 10 ? ns ras hold time from cas precharge t rhcp 40 ? ns
fedd51x17400f-03 1 semiconductor msm51x17400f 7/13 ac characteristics (2/2) (v cc = 2.0v 0.15v, ta = ?10 to 70c) note 1,2,3 msm51x17400 f-10 parameter symbol min. max. unit note ras to cas delay time t rcd 25 80 ns 5 ras to column address delay time t rad 20 50 ns 6 row address set-up time t asr 5 ? ns row address hold time t rah 15 ? ns column address set-up time t asc 5 ? ns column address hold time t cah 20 ? ns column address to ras lead time t ral 50 ? ns read command set-up time t rcs 5 ? ns read command hold time t rch 5 ? ns 8 read command hold time referenced to ras t rrh 5 ? ns 8 write command set-up time t wcs 5 ? ns write command hold time t wch 20 ? ns write command pulse width t wp 20 ? ns write command to ras lead time t rwl 20 ? ns write command to cas lead time t cwl 20 ? ns data-in set-up time t ds 5 ? ns data-in hold time t dh 20 ? ns cas active delay time from ras precharge t rpc 10 ? ns ras to cas set-up time ( cas before ras ) t csr 10 ? ns ras to cas hold time ( cas before ras ) t chr 15 ? ns
fedd51x17400f-03 1 semiconductor msm51x17400f 8/13 notes: 1. a start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5ns. 3. v ih (min.) and v il (max.) are reference levels for measur ing input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 30pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t off (max.) and t oez (max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. t rch or t rrh must be satisfied for a read cycle.
fedd51x17400f-03 1 semiconductor msm51x17400f 9/13 timing chart read cycle write cycle (early write) t off t clz t cac t oea t asc t rrh t rah t asr t rad t ral t crp t cah t crp t rcd t rc t ras t rp t csh t rsh t cas t rac t aa t rcs t roh t rch t oez row column valid data-out o p en ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v oh v ol ?h? or ?l? t crp t rp t rwl valid data-in t dh t ds t wcs t wch t cwl t asr t rah t asc t rc t ras row t csh t crp t rcd t rsh t cas column t cah t rad t ral t wp ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v ih v il ?h? or ?l? open
fedd51x17400f-03 1 semiconductor msm51x17400f 10/13 fast page mode read cycle t clz t oea t rcs t oez t cac t rrh t rch t rcs t cpa t rch t aa t oea t off t oez t clz t off t cah t cas t ral t asc t rsh t cp t cah t rp t rhcp column t crp t pc t off t cac t csh t cac t oez t rac t oea t rch t cpa t aa t aa t cah t asc t rah t rad t rcs t asr t asc t cp t cas t rasp t cas t rcd t crp t clz valid data-out row column column ra s v ih v il ca s v ih v il address v ih v il w e v ih v il o e v ih v il dq v oh v ol ?h? or ?l? valid data-out valid data-out
fedd51x17400f-03 1 semiconductor msm51x17400f 11/13 fast page mode write cycle (early write) cas before ras refresh cycle t wp t cwl t wch t asc t cp t pc t rasp column t ral t crp t asc t cah t cah t cas t rsh t cp t cas t rp t rhpc column t wp t wch t dh t ds t dh t ds valid * data-in t wcs t wcs valid * data-in t cwl t csh t rad t asr t asc t rah t rcd t crp t cas t cah row column t wp t rwl t wch t cwl t dh t ds t wcs valid * data-in ?h? or ?l? ra s v ih v il ca s v ih v il address v ih v il w e v ih v il dq v ih v il note: oe = ?h? or ?l? t wrh t wrp t wrp t off t rpc t rp t rc t ras t chr t csr t rp t cp t rpc ras v ih v il cas v ih v il v oh v ol dq o p en note: oe , address = ?h? or ?l? we v ih v il ?h? or ?l?
fedd51x17400f-03 1 semiconductor msm51x17400f 12/13 revision history page document no. date previous edition current edition description fedd51x17400f-01 aug., 2001 ? ? final edition 1 fedd51x17400f-02 feb., 2002 1, 4, 5, 6, 7 1, 4, 5, 6, 7 changed vccmax. from 2.4v to 2.15v fedd51x17400f-03 aug, 2002 1, 2 1, 2 deleted soj package
fedd51x17400f-03 1 semiconductor msm51x17400f 13/13 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are refl ected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to , operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, ne glect, improper installati on, repair, alteration or accident, improper handling, or unusual physi cal or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s in dustrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for us e in any system or application that requires special or enhanced quality and reliability char acteristics nor in any system or ap plication where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, tr affic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of de termining the legality of export of these products and will take appropriate and necessary st eps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2002 oki electric industry co., ltd.

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